A successive approximation register analog-to-digital converter (SAR ADC) is a type of analog-to-digital converter that converts a continuous analog waveform into a discrete digital representation by a search scheme. One of the most common implementations of SAR ADC, the switched-capacitor (or charge-redistribution) SAR ADC, uses a switched-capacitor network composed of a plurality of capacitors. The capacitors are individually switched on the basis of the search scheme for obtaining the approximation of the analog input.
In recent years, the operation speed of SAR ADCs has been improved with the scaling of complementary metal oxide semiconductor (CMOS) technology. SAR ADCs may achieve a few hundreds mega-samples per second (MS/s) with 8-bit to 10-bit resolution. The signal-to-noise ratio (SNR) of high-speed SAR ADCs is mainly dominated by comparator noise and usually limited to 50 dB-60 dB. The power consumption of the comparator may be increased exponentially to thereby suppress the comparator noise in a limited comparison time to improve the SNR. Concerning the conventional noise-tolerant SAR ADC, it reduces comparator power in first bit-cycles by using a coarse comparator, but the fine comparator in the remaining bit-cycles still consumes significant power to achieve an SNR more than 60 dB. Concerning the conventional SAR-assisted pipelined ADC, it can release the requirement of a low noise comparator, but will induce gain errors between inter-stages. The gain calibration increases the design complexity. Further, the amplifier and back-end stages result in extra noise and area to the ADCs. Concerning the conventional fully-differential digital slope ADC, it is inherently low-noise due to quantizing the signal in the time domain, but the hardware grows exponentially with resolution and the maximum conversion rate is halved with each additional bit of resolution. Hence, this conventional fully-differential digital slope ADC is unattractive for resolution higher than 8 bits.
Thus, there is a need for an innovative ADC design which is capable of achieving lower power consumption, lower noise, and higher resolution.